ASIC Design Hardware Engineer - SDC/STA (Hybrid)
Core
Develop timing constraints (SDC) and validate them using industry-standard tools to ensure full-chip timing closure for next-generation networking chips.
Role type
Senior ASIC Design Hardware Engineer (SDC/STA)
Builds
Unified silicon architecture for web scale and service provider networks
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SDC/STA tools, Synopsys DC/DCG/FC, Verilog/SystemVerilog, TCL scripting, digital design concepts (clocking, timing exceptions, async boundaries), microarchitecture, RTL implementation
Preferred skills
Cross-functional collaboration, problem-solving, technical communication, innovative thinking
Technologies
Synopsys DC/DCG/FC, Primetime, Timevision, TCM, Shell, Perl
Responsibilities
Develop block level and full-chip SDCs, collaborate with physical design and DFT teams to close timing, review clocking diagrams and SDCs, contribute to full-chip clocking design and documentation, help develop methodologies to promote block level SDCs to full-chip
Seniority
Senior, hands-on IC
