ASIC Engineer - SDC
Core
Develop full-chip timing constraints (SDC) and drive Static Timing Analysis (STA) for complex networking System-on-Chip (SoC) designs.
Role type
Senior ASIC Engineer (Timing Closure)
Builds
Full-chip SoC designs for Cisco core Switching, Routing, and Wireless products
Domain
Semiconductor / ASIC Design / Networking Hardware
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip SDC constraint development, Static Timing Analysis (STA), RTL design analysis, clocking architecture definition, third-party IP integration, timing-driven RTL improvement
Preferred skills
Large SoC multi-clock domain expertise, micro-architectural improvement recommendations, constraint analysis tools (TCM, CCD), CDC analysis tools, engineering scripting (Python, Perl, TCL)
Technologies
Synopsys PrimeTime, Cadence Tempus, Synopsys TCM, Cadence CCD, SpyGlass CDC
Responsibilities
Own and develop full-chip timing constraints across functional and test modes, Drive STA and partner with RTL/physical design/DFT teams to resolve timing issues, Partner with RTL designers to achieve timing convergence, Define and maintain clocking architectures and constraint models, Integrate and validate timing constraints from third-party IP vendors, Contribute to timing closure and silicon readiness across multiple modes and corners
Seniority
Senior, hands-on IC
