ASIC Engineering Technical Leader- DFT
Required skills
Bachelor's or a Master's Degree in Electrical or Computer Engineering, Prior experience in post-silicon debug experience from first silicon to production, Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan, Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime, Prior experience working with Gate level simulation, debugging with VCS and other simulators
Preferred skills
Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification, DFT CAD development - Test Architecture, Methodology and Infrastructure, Test Static Timing Analysis, Post silicon validation using DFT patterns, Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
Technologies
TestMax, Tetramax, Tessent tool sets, PrimeTime, VCS, Jtag protocols, Scan and BIST architectures, memory BIST and boundary scan, ATPG, Gate level simulation
Responsibilities
Responsible for defining and implementing post-silicon strategies, Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs, Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL, Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows, Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies, The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship
Seniority
Technical Leader
Domain
ASIC Engineering, DFT, Networking Hardware, Silicon Architecture
