ASIC Engineer | Physical Design | 4+ Years |
Core
Creating next generation state-of-the-art networking chips in advanced process nodes by driving the backend process through the entire RTL to GDS implementation flow.
Role type
Senior ASIC Physical Design Engineer
Builds
Networking chips for Enterprise and Service Provider solutions
Domain
Semiconductor / Networking / Advanced Process Nodes (sub 16/14/7/5/3nm)
Deliverable
production ML models | product features | infrastructure
Required skills
Hierarchical floor planning, Place & route, Timing closure, Power integrity analysis, Physical verification, Equivalence checks, Hard IP integration, Large design implementation (>100M gates), STA setup and convergence, Timing ECO implementation, Automation script development
Preferred skills
Methodology improvement for physical design tools and flows, CTS strategy development, Multi-Mode and Multi-corner design sign-off, Debugging implementation issues, Evaluation of timing methodologies across technology nodes
Technologies
EDA tools (Tweaker/Primetime), STA tools, Sub-16nm to 3nm process nodes
Responsibilities
Drive hierarchical floor planning, place & route, and timing closure; Perform power integrity analysis and physical verification; Execute timing ECO implementation strategies; Develop automation scripts for STA tools; Collaborate with RTL, DFT, and tool/flow owners to improve methodologies.
Seniority
Senior, hands-on IC
