ASIC Engineer || SDC || Design and Timing Constraints | Exp 8+ years
Core
Define, design, and verify ASIC subsystems for Cisco networking platforms, focusing on timing constraints and physical design closure.
Role type
Senior ASIC Engineer (SDC/Timing Constraints)
Builds
Next-generation networking chips and ASIC subsystems
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | infrastructure
Required skills
Static Timing Analysis (STA), SDC/DTA tool proficiency, clock group management, Verilog/System Verilog, Synthesis tools (Synopsys DC/DCG/FC), RTL design, clocking diagrams
Preferred skills
TCM (Timing Constraint Manager), CCD (Conformal Constraint Designer), Spyglass CDC/Glitch analysis, Formal Verification (Synopsys Formality, Cadence LEC), Python/Perl/TCL scripting
Responsibilities
Collaborate with front-end and back-end teams to refine design and timing constraints; develop next-generation networking chips; oversee full-chip SDCs and work with physical design and DFT teams; mentor RTL design owners on SDC development; create full-chip clocking diagrams and documentation
Seniority
Senior, hands-on IC
