ASIC DFT Engineering Technical Leader | 12+ years, Bangalore
Core
Lead Design-for-Test (DFT) engineering for Cisco Silicon One ASICs, defining testability features and driving quality processes from RTL through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Leader
Builds
Next-generation networking chips (switching, routing, wireless) for enterprises, service providers, and public sector.
Domain
Semiconductor hardware design, ASIC implementation, networking infrastructure.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture (Scan, BIST, JTAG), ATPG, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), System Verilog, Gate-level simulation (VCS), Post-silicon debug, ATE pattern development, Scripting (Tcl, Python/Perl), RTL/Physical design collaboration.
Preferred skills
Custom DFT IP development, DFT CAD infrastructure, Test Static Timing Analysis, Functional verification.
Technologies
VCS, TestMax, Tetramax, Tessent, PrimeTime, Tcl, Python, Perl, JTAG, BIST, ATPG.
Responsibilities
Implement DFT features for ATE and in-system test; Develop innovative DFT IP and integrate test logic with RTL; Collaborate with design, verification, and physical design teams; Drive DFT and quality processes through implementation and post-silicon validation; Craft debug solutions with minimal mentorship.
Seniority
Senior, hands-on IC technical leader
