ASIC DFT Engineer - 4 to 8 yrs
Core
Implementing Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics for Cisco's core switching, routing, and wireless silicon platforms.
Role type
ASIC DFT Engineer
Builds
Silicon devices (bare die & stacked die) with integrated testability features for enterprise and service provider networks.
Domain
Networking hardware / Silicon engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT IP development, Jtag protocols, Scan and BIST architectures, memory BIST, boundary scan, ATPG, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), System Verilog, gate-level simulation, VCS debugging
Preferred skills
Post-silicon validation, ATE pattern generation (P1687), Tcl/Python/Perl scripting
Technologies
TestMax, Tetramax, Tessent, PrimeTime, VCS, System Verilog
Responsibilities
Implement DFT features for ATE and in-system test; Develop innovative DFT IP for full chip design integration; Collaborate with design/verification/PD teams for test logic validation; Create re-usable test and debug strategies for new silicon models; Debug designs with minimal mentorship
Seniority
Mid-level IC (4-8 years experience)
