ASIC Design Verification Engineer | UVM | Exp 8+ Years
Core
Define, design, and verify ASIC and ASIC subsystems for Cisco platforms, focusing on power, performance, and area goals.
Role type
Senior ASIC Design Verification Engineer
Builds
ASIC subsystems and verification environments for high-volume Cisco hardware products
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models
Required skills
ASIC design verification, UVM, SystemVerilog, testbench development, functional coverage, gate-level simulation, Perl, Python
Preferred skills
P4, Forwarding logic, Emulation (Veloce/Palladium/Zebu/HAPS), Formal verification, PCIe, Ethernet, RDMA, TCP
Technologies
UVM, SystemVerilog, Perl, Python, Veloce, Palladium, Zebu, HAPS, iev, vc formal
Responsibilities
Architect DV environment infrastructure, develop test plans with constraint random and advised stimulus, ensure verification coverage, perform gate-level simulations, debug post-silicon issues, manage ASIC bring-up
Seniority
Senior, hands-on IC (8+ years experience)
