Standard Cell Design Methodology & Flow Engineer
Core
Designing standard cell libraries and production flows for deep submicron processor designs, integrating custom digital circuits and library development.
Role type
Standard Cell Design Methodology & Flow Engineer
Builds
Standard cell libraries, production flows, and custom digital blocks for processors
Domain
Semiconductor / Deep Submicron Digital Design
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, Python/TCL/Perl, EDA tools (synthesis, place-route, DRC/LVS), timing/power analysis, data analysis, machine learning, device physics, foundry ecosystem knowledge
Preferred skills
Library characterization, timing/power/CCS noise/variation modeling, Liberty formats, Spice simulation, static timing analysis, DFT/scan concepts, flow automation, FE modeling, VHDL
Technologies
Verilog, SystemVerilog, Python, TCL, Perl, Spice, Liberty, EDA tools
Responsibilities
Interface with internal CAD teams and foundries for PDK requirements; collaborate on new process requirements and tool/flow enablement; implement digital blocks and run verification; analyze circuit trends in timing, power, and area using data analysis and ML models
Seniority
Mid-Senior, hands-on IC
