CAD Engineer – EMIR Signoff
Core
Ensure verification and analysis on complex mixed-signal designs prior to tapeout, focusing on power/EMIR analysis and signoff methodologies.
Role type
Senior IC signoff engineer (mixed-signal/SoC)
Builds
High-performance, power-efficient system-on-chip (SoC) processors for Apple
Domain
Semiconductor design, mixed-signal circuits, power integrity
Required skills
EMIR analysis (static/dynamic), gate and transistor-level signoff, EDA flow setup, Perl/Python scripting, mixed-signal circuit design, IP reuse, power switch modeling, signal EM analysis
Preferred skills
AI/ML and LLM-driven techniques for EDA automation, anomaly detection, Redhawk/Voltus/Totem tool expertise, CMOS analog design
Technologies
Redhawk, Voltus, Totem, Perl, Python
Responsibilities
Define signoff requirements early in the project lifecycle, partner with Design/CAD/Technology teams to confirm EDA flows, interface with design groups for enablement and debug requests, apply hands-on experience in power/EMIR analysis to refine signoff methodologies
Seniority
Senior, hands-on IC
