Wireless SOC Verification Engineer
Core
Pre-silicon RTL verification of complex Wireless SOCs, including block and top-level verification, using UVM methodologies and coverage-driven test cases.
Role type
Design Verification Engineer (Wireless SOC)
Builds
Wireless SOCs for Networking in iPhones
Domain
Semiconductor / Silicon Design / Wireless Protocols
Required skills
System Verilog, Verilog, UVM, RTL verification, coverage-driven verification, multi-chip SOC debug architecture, high-speed layered protocols, low-power driven architecture, FW-HW interactions
Preferred skills
Formal Verification, Low Power Verification, ASIC & SOC DV experience, Expertise in SystemVerilog coding and UVM methodology
Technologies
UVM, System Verilog, Verilog, UPF, PCIe, DDR, USB, PLL, DMA, Memory Controller
Responsibilities
Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level; Create coverage driven verification plans from specifications to achieve coverage targets; Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations; Work closely with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design; Understand details of High Efficiency SOC Architecture, standard SOC peripherals, Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes; Work with DV methodology architects to improve verification metrics
Seniority
Entry to Mid-level, hands-on IC
