CAD Logic Equivalence Checking (LEC) Engineer - m/f/d
Core
Develop, deploy, and support logical equivalence checking (LEC) methodologies to ensure functional correctness between RTL, synthesized netlists, and post-implementation designs for complex SoCs.
Role type
Senior IC VLSI verification engineer (equivalence checking)
Builds
Scalable, robust sign-off flows for chip design automation
Domain
Semiconductor hardware design / VLSI / EDA
Required skills
RTL design, Synthesis and netlist transformations, Low-power design (UPF), LEQ tools (Cadence Conformal, Synopsys Formality), Debugging, Scripting (TCL, Python)
Preferred skills
Power-aware LEQ, Synthesis and PnR flows, Large-scale SoC environments, ECO flows, EDA vendor collaboration
Technologies
Cadence Conformal, Synopsys Formality, UPF, TCL, Python
Responsibilities
Own and maintain LEQ sign-off methodology across RTL-to-GDS flows; Develop and support flows using tools such as Cadence Conformal and equivalent industry solutions; Drive power-aware equivalence checking including CPX flows; Enable ECO flows, ensuring safe and correct implementation of late-stage design changes; Debug equivalence failures and perform root-cause analysis across RTL, synthesis, and PnR stages; Collaborate with design, synthesis, PD, and power teams to resolve mismatches and improve convergence; Optimize runtime, capacity, and scalability of LEQ flows for large SoCs; Define best practices, guidelines, and automation for LEQ usage across projects; Partner with EDA vendors to resolve tool issues and drive feature improvements
