CPU Design Timing Engineer
Core
Responsible for timing closure of high-performance CPU designs, collaborating with implementation and RTL teams to ensure timing constraints are met.
Role type
Senior IC CPU Design Timing Engineer
Builds
High-performance CPU microarchitectures
Domain
Semiconductor / CPU Design
Required skills
Static timing analysis, timing flow development, scripting (TCL, Perl, Python), physical design verification (LEC, DVS), multi-clock domain handling, noise/OCV/derate methodology
Preferred skills
High-performance CPU implementation experience, CPU microarchitecture knowledge, physically aware synthesis, place & route flows, cross-talk analysis
Technologies
Primetime, Tempus, physically aware synthesis tools, place & route tools
Responsibilities
Develop timing flows with CAD teams, script analysis flows for efficiency, drive timing closure with micro-architects and implementation engineers, analyze timing for 1 GHz+ designs with multiple clock/power domains
Seniority
Mid-Senior, hands-on IC
