Physical Synthesis CAD Engineer
Core
Develop and validate physical synthesis techniques and flows to optimize performance, power, and area (PPA) for Apple Silicon processors.
Role type
Senior IC physical synthesis CAD engineer
Builds
Custom synthesis tools, flows, and methodologies for high-performance, low-power processor architectures
Domain
Semiconductor design / Physical Design / EDA
Deliverable
production ML models | product features
Required skills
Physical synthesis, RTL optimization, PNR flow, Static Timing Analysis (STA), Power analysis, Scripting (TCL, Python, Perl), EDA tool integration
Preferred skills
Fusion Compiler, Genus, UPF, Logical Equivalence Checking (Conformal LEC, Formality), Linting, Place and Route tools
Technologies
Fusion Compiler, Genus, UPF, Conformal LEC, Formality
Responsibilities
Develop breakthrough physical synthesis techniques and validate them with full implementation flows Apply advanced RTL optimization techniques to achieve substantial improvements in PPA Partner with design teams to define optimal methodologies and flows Create custom tools and ML-based methodologies for challenging design problems Influence EDA vendor tool development by solving hardest problems Deploy solutions across multiple critical Apple Silicon projects