SoC Physical Design Engineer, STA/Timing
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs using state-of-the-art process technology.
Role type
SoC Physical Design Engineer (STA/Timing)
Builds
Next-generation Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
STA, timing closure, Perl scripting, TCL scripting, timing path analysis, ECO implementation, circuit modeling, SPICE models, worst-case corner selection, noise/crosstalk/OCV analysis
Preferred skills
Hands-on STA experience, sub-micron technology timing expertise, timing infrastructure implementation
Technologies
Perl, TCL
Responsibilities
Debug constraints and facilitate logic changes to improve timing; Create and maintain scripts and methodologies for analysis and runs; Deep analysis of timing paths to identify key issues; Implement timing infrastructure; Help create timing ECOs for project tapeout; Create documentation and help with guidelines/specs.
