SoC Physical Design Engineer, STA/Timing
Core
Physical implementation of SoC design partitions from netlist to tapeout, focusing on timing closure and debug.
Role type
SoC Physical Design Engineer (STA/Timing)
Builds
Highly complex SoCs using state-of-the-art process technology
Domain
Semiconductor / SoC Physical Design
Required skills
Static Timing Analysis (STA), noise/crosstalk/OCV analysis, timing ECO implementation, Perl/TCL scripting, timing path analysis, timing infrastructure implementation
Preferred skills
Large high-performance SoC design in sub-micron technologies, timing closure methodologies, circuit modeling (SPICE), worst-case corner selection, ECO techniques
Technologies
Perl, TCL, SPICE
Responsibilities
Debug constraints and facilitate logic changes to improve timing, create timing ECOs for tapeout, implement timing infrastructure, analyze timing paths to identify key issues, create and maintain analysis scripts and methodologies
Seniority
Entry-level, hands-on IC
