Gate-level SigEM/SEB/FIT CAD Engineer
Core
Develop and refine gate-level and transistor-level design methodologies for electromigration (EM), static error band (SEB), failure in time (FIT), and thermal analysis to ensure silicon integrity.
Role type
Senior IC physical design verification engineer (EM/SEB/FIT/Thermal)
Builds
IP / SOC signal EM analysis flows, 3DIC thermal integrity solutions, and sign-off verification methodologies for clock and data nets.
Domain
Semiconductor manufacturing / Physical Design Verification
Required skills
EM/SEB/FIT/SHE/Thermal methodologies, EDA tool qualification, Tcl/Python/Perl scripting, correlation studies with failure analysis, advanced packaging knowledge
Preferred skills
Current density calculations, EM extraction and simulation, multi-user environment software development, AI/ML-driven CAD workflows
Technologies
Voltus, Voltus-Fi, RedHawk-SC, Totem
Responsibilities
Develop comprehensive EM/SEB/thermal methodologies across advanced node designs; Implement customized solutions scaling with accuracy and capacity; Maintain EM/SEB/thermal flow from concept through sign-off; Collaborate with Physical Design, Clock/Signal Integrity, and Power teams on trade-offs; Develop and validate EM/thermal rule decks for clock trees and high-speed data paths; Work with EDA vendors and foundries for tool qualification and model development; Participate in correlation studies between EM tools and silicon failure data
Seniority
Senior, hands-on IC
