STA Engineer
Core
Lead full-chip and block-level timing closure for high-end mobile SoCs, developing verification methodologies and resolving complex timing issues across deep sub-micron technologies.
Role type
Senior IC STA Engineer (SoC)
Builds
High-performance System-on-Chip (SoC) hardware for mobile applications
Domain
Semiconductor / ASIC Design / Mobile Hardware
Required skills
Full-chip timing closure, Block-level timing closure, Timing verification flows, Timing constraint generation, Deep sub-micron technology expertise, Complex timing issue resolution
Preferred skills
Digital design fundamentals, Scripting (TCL, Perl), ASIC timing concepts, Primetime tool proficiency, Front-end design tools (Synthesis, LEC), Constraint analysis (Synopsys GCA), Timing corners/process variations/signal integrity
Technologies
Primetime, Synopsys GCA, TCL, Perl, Synthesis, LEC
Responsibilities
Own full-chip and block-level timing closure throughout the project lifecycle, Develop and maintain timing verification methodologies and flows, Generate block and full-chip timing constraints, Collaborate with multi-functional teams to resolve complex timing issues in major SoC building blocks
Seniority
Senior, hands-on IC
