STA Engineer
Core
Leading edge IP development and SoC timing closure/constraints ownership throughout the entire project.
Role type
ASIC Static Timing Analysis Engineer
Builds
High quality IP deliverables for System on Chip (SoC) products
Domain
Semiconductor hardware design
Required skills
Digital design fundamentals, ASIC design timing concepts, scripting languages (TCL, Python, Perl), STA tools (Primetime), timing constraints, timing corners/modes, front-end tools (Synthesis, Logic equivalence checks)
Preferred skills
None explicitly stated as preferred beyond the minimum qualifications
Technologies
Primetime, TCL, Python, Perl
Responsibilities
Execute design and integration tasks for high quality IP deliverables, collaborate with SoC Design, Verification, DFT, Architecture, and Physical Design teams, define and improve front-end design methodologies, develop and maintain methodology and flows related to timing analysis
Seniority
Entry-level (0 years experience)
