STA Engineer
Core
Leading edge IP development and SoC timing closure/constraints ownership throughout the entire project.
Role type
Senior IC ASIC Static Timing Analysis Engineer
Builds
High quality IP deliverables for Apple hardware products
Domain
Semiconductor / ASIC Design
Required skills
Digital design fundamentals, ASIC design timing concepts, Scripting (TCL, Python, Perl), STA tools (Primetime), Timing constraints, Timing corners/modes, Front-end tools (Synthesis, Logic equivalence checks)
Preferred skills
Full chip and block level timing closure, CAD and Flow team collaboration, Methodology development
Responsibilities
Execute design and integration tasks for high quality IP deliverables, Define and improve front-end design methodologies, Develop and maintain methodology and flows related to timing analysis
Seniority
Entry-level, hands-on IC
