Timing Design Engineer
Core
ASIC Static Timing Analysis (STA) engineer responsible for timing sign-off, flow development, and constraint management for SoC designs.
Role type
Senior IC ASIC STA Engineer
Builds
Production ASIC chips with verified timing closure
Domain
Semiconductor / ASIC Design
Required skills
ASIC timing closure flow, STA tools (Primetime), timing constraints (SDC), scripting (Tcl, Perl), synthesis/DFT/backend methodology, process variations, signal integrity
Preferred skills
IP and block-level timing ownership, RTL/clock structure understanding, flow innovation, pessimism reduction in timing analysis
Responsibilities
Develop STA and sign-off flows, manage timing constraints from synthesis to sign-off, collaborate with RTL and physical design teams, verify timing constraints, innovate timing methodologies
Seniority
Senior, hands-on IC
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