STA Design Engineer - Static Timing Analysis - Cork, Ireland
Core
Perform static timing analysis, develop timing constraints, and optimize timing performance for high-performance, low-power ASIC solutions and SOCs.
Role type
Senior IC static timing analysis engineer
Builds
High-performance, low-power ASIC solutions and Snapdragon Cores/SOCs
Domain
Semiconductor / ASIC Design
Required skills
Static timing analysis (STA), timing closure, ASIC design flows (RTL-to-GDS), automation scripting (Python/TCL/Perl), gate-level PNR netlist analysis, ECO generation, cross-functional collaboration
Preferred skills
Design for Parametric Yield, circuit simulation tools, extraction tools
Technologies
PrimeTime, PrimeShield, Tempus, Tweaker, PrimeClosure, PTECO
Responsibilities
Perform STA and timing closure for complex cores and full-chip SOCs, Enhance techniques and methodologies for STA and timing closure, Drive accuracy of timing closure and static/dynamic flows, Ensure compliance with timing signoff checklists, Automate timing and power data mining and processing, Resolve issues in all phases of development
Seniority
Senior, hands-on IC
