Sr. Staff Engineer - Physical Design
Core
Drive the complete RTL-to-GDSII physical design flow for next-generation, high-performance System-on-Chips (SoCs), focusing on aggressive Power, Performance, and Area (PPA) metrics.
Role type
Senior Individual Contributor Physical Design Engineer
Builds
High-performance SoCs for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor / VLSI Physical Design
Required skills
RTL-to-GDSII flow ownership, PPA optimization, Static Timing Analysis (STA), Physical & Formal Verification, Tcl/Python/Perl scripting, EDA tool expertise
Preferred skills
Mentoring junior engineers, multi-voltage domain design, power gating strategies (via careerplan.io/jobs/744000153699479-sr-staff-engineer-physical-design-at-renesas-electronics)
Technologies
Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk
Responsibilities
Execute floor planning, synthesis, placement, CTS, and routing; resolve setup/hold violations and signal integrity issues; perform DRC, LVS, EMIR, and Equivalence Checking; collaborate with RTL, DFT, and Signoff teams to iterate designs.
Seniority
Senior, hands-on IC
