SIPI Architect for High-Speed SerDes
Core
Define and own end-to-end signal and power integrity (SIPI) architecture and strategy for cutting-edge high-speed SerDes interconnects, ensuring robust performance from silicon to system.
Role type
Senior IC SIPI Architect (High-Speed SerDes)
Builds
High-performance interconnect solutions for large-scale systems (data center, HPC)
Domain
Semiconductor / High-Speed Interconnects / System-Level Co-Design
Required skills
End-to-end SIPI architecture, System-level trade-off analysis, Statistical and time-domain simulation, SerDes TX/RX equalization, Channel modeling and link budget analysis, Cross-functional technical leadership, Advanced packaging knowledge, Power integrity (PDN) and thermal co-design
Preferred skills
MS or PhD in Electrical Engineering, Expertise in 112G/224G+ SerDes, Experience with Ethernet/PCIe/UAL/CXL standards, Knowledge of co-packaged optics (CPO), 2.5D/3D integration experience
Technologies
SerDes, Ethernet, PCIe, UAL, CXL, COM, 2.5D/3D integration
Responsibilities
Define SIPI architecture and strategy for high-speed SerDes links, Drive technical direction and build consensus across circuit design, packaging, and system hardware teams, Lead system-level trade-off analysis to optimize performance, power, and cost, Influence technology roadmap for future interconnect technologies, Oversee comprehensive modeling, simulation, and silicon correlation, Develop next-generation SIPI methodologies and best practices
Seniority
Senior, hands-on IC with strategic influence
