Design Verification Engineer
Core
Design Verification Engineer ensuring bug-free first silicon for IP designs and SoC components by developing verification environments, test plans, and methodologies.
Role type
Senior IC design verification engineer (first silicon)
Builds
Pre-silicon verification environments, test-benches, and test plans for IP and SoC designs
Domain
Semiconductor hardware design and verification
Required skills
SystemVerilog, UVM, test-plan development, verification environment development, debug, coverage analysis, LLM usage for verification, scripting (Python/Perl/TCL)
Preferred skills
Power-aware verification (UPF), formal verification, emulation technologies, serial/parallel protocol knowledge (PCIe, USB, DDR), OOP
Technologies
SystemVerilog, UVM, simulators, waveform viewers, build automation tools, coverage collection tools, LLMs
Responsibilities
Study design specifications and create test plans; Develop infrastructure in SystemVerilog/UVM to stress the design; Develop and fix failures from regressions and close bugs; Use LLMs to optimize verification execution; Develop scalable and portable verification environments including stimulus, checkers, and assertions; Track and report DV progress using metrics like bugs and coverage.
Seniority
Senior, hands-on IC
