Design Verification Engineer
Core
Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors for large-scale SoC verification.
Role type
SoC verification engineer
Builds
Verification infrastructure and test environments for System-on-Chip designs
Domain
Semiconductor hardware design
Required skills
SystemVerilog, UVM, coverage-driven verification, formal methods, hardware acceleration, Perl, Python, Verilog, C, C++, TCL
Preferred skills
Storage IP knowledge, control-oriented design expertise
Technologies
SystemVerilog, UVM, Perl, Python, Verilog, C, C++, TCL
Responsibilities
Develop verification test plans and tools, create test benches and protocol monitors, generate high-coverage stimulus vectors, collaborate with design teams to ensure timely delivery
Seniority
Mid-Senior, hands-on IC
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