Pre-Silicon Verification Engineer - Hod Hasharon
Core
Develop block and cluster level test environments, test plans, and coverage for advanced high-speed products using SystemVerilog UVM and Formal verification.
Role type
Pre-Silicon Verification Engineer
Builds
Test environments and verification coverage for high-speed ASIC products
Domain
Semiconductor / ASIC Design
Required skills
SystemVerilog UVM, Formal verification, Test environment development, Test planning, Coverage analysis, ASIC design knowledge
Preferred skills
Networking products experience, Advanced degree (Master's/PhD)
Technologies
SystemVerilog, UVM, Formal verification tools
Responsibilities
Develop block and cluster level test environments, Create test plans and coverage strategies, Collaborate with Design and Architecture teams, Utilize Formal verification environments
Seniority
Mid-Senior, hands-on IC
