STA Lead (m/f/d)
Core
Leading a local team responsible for SoC design timing and synthesis, ensuring timing closure from synthesis to sign-off for Analog Mixed Signal IPs.
Role type
Senior IC ASIC Design Lead (Timing & Synthesis)
Builds
Analog Mixed Signal IPs and SoCs
Domain
Semiconductor / ASIC Design
Required skills
ASIC timing closure flow, STA tools (Primetime), timing constraints (SDC), scripting (Tcl, Perl), synthesis methodology, DFT, backend methodology, team leadership
Preferred skills
Bachelor's/Master's in Electrical Engineering
Technologies
Primetime, SDC, Tcl, Perl
Responsibilities
Develop and own full chip, IP, and block level timing constraints; collaborate with RTL designers to understand design intent and clock structure; work with CAD and Physical Design teams to close timing; innovate timing constraints and flows to facilitate closure; improve synthesis results and methodologies; lead the local team to deliver high-quality collaterals on time.
Seniority
Senior, hands-on IC with team leadership
