Cellular ASIC Design Engineer
Core
Develop and optimize design and implementation methodology for high-performance, power-efficient cellular chips and system-on-chips (SoC) in advanced process technologies.
Role type
Senior IC ASIC design methodology engineer
Builds
Next-generation cellular SoCs for Apple devices
Domain
Consumer electronics / Semiconductor / VLSI
Deliverable
production ML models
Required skills
VLSI design flow expertise, RTL to GDSII flows, Power/Performance/Area/Cost optimization, Design Technology Co-optimization, Python/TCL/Perl scripting, STA methodology, Spice simulation, DFT methodology
Preferred skills
Physical design implementation, Metal stack optimization, Early tech node analysis, Data science/ML analytics for design optimization
Technologies
Synopsys DC/DCT/DCG/Genus/Oasis, Cadence ICC2/Fusion/Innovus/Aprisa, Synopsys PT/PT-SI/Tempus, RedHawk/SeaHawk/Voltus, Hspice/Finesim/AFS/Spectre/Infinisim
Responsibilities
Establish design guidelines and standards for synthesis, place-and-route, and signoff processes; Develop and optimize EDA tool flows for timing closure and productivity; Perform design technology co-optimization analysis and Spice simulations for PVT corners; Develop voltage scaling and power optimization methodologies; Collaborate with IP and process technology teams for advanced node bring-up; Automate design flows using scripting languages.
Seniority
Senior, hands-on IC
