Cellular ASIC Design Engineer
Core
Develop and optimize design and implementation methodology for high-performance, power-efficient cellular chips and system-on-chips (SoC) at the block/IP and system levels.
Role type
Senior IC design engineer (ASIC methodology & physical design)
Builds
Next-generation cellular SoCs for Apple devices
Domain
Consumer electronics / Semiconductor / Advanced process nodes (3nm, 2nm)
Deliverable
production ML models
Required skills
VLSI design, RTL to GDSII flows, Power/Performance/Area/Cost optimization, Design Technology Co-optimization, EDA tool flows (synthesis, P&R, signoff), Python/TCL/Unix scripting, Spice simulation, STA methodology
Preferred skills
Physical design challenges, Metal stack optimization, Early tech node analysis, Data science/ML analytics for design databases
Technologies
DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, PT/PT-SI/Tempus, Hspice/Finesim/AFS/Spectre/Infinisim, RedHawk/SeaHawk/Voltus
Responsibilities
Establish design guidelines and standards for synthesis, place-and-route, and timing closure; Develop and optimize EDA tool flows and automation scripts; Perform design technology co-optimization analysis and Spice simulations; Develop voltage scaling and power optimization methodologies; Collaborate with IP and process technology teams for advanced node bring-up.
Seniority
Senior, hands-on IC
