IP Design Verification Engineer
Core
Design Verification Engineer ensuring bug-free first silicon for IP designs through pre-silicon verification phases.
Role type
Senior IC design verification engineer
Builds
Fully functional first silicon IP designs
Domain
Semiconductor / Digital Logic Design
Required skills
Digital logic design verification, SystemVerilog, UVM, verification environment development, stimulus generation, checker development, assertions, coverage analysis, debug, gate-level simulation, verification tools (simulators, waveform viewers, automation)
Preferred skills
Python, Perl, TCL, serial/parallel protocols (PCIe, DRAM), formal verification, C/C++, lab hands-on debug
Technologies
SystemVerilog, UVM, Python, Perl, TCL, PCIe, DRAM
Responsibilities
Develop detailed test and coverage plans based on micro-architecture; Develop verification methodology suitable for the IP; Develop verification environment including stimulus, checkers, assertions, trackers, and coverage; Perform debug and sign-off for RTL freeze and tape-out.
Seniority
Senior, hands-on IC
