Principal D2D SerDes & Analog Layout Design Engineer
Core
Define physical implementation strategy and execute complex D2D SerDes and analog/mixed-signal subsystems in advanced process technologies from architecture through tapeout.
Role type
Principal D2D SerDes & Analog Layout Design Engineer
Builds
Production-ready D2D and analog IP collateral (GDS/OASIS, LEF, integration views) for SoC and package integration
Domain
Semiconductor, Advanced Node Analog/Mixed-Signal, Die-to-Die Interfaces
Required skills
Advanced node analog/mixed-signal layout, D2D interface design, Cadence Virtuoso, Calibre verification, Python/SKILL/TCL automation, EMIR/reliability analysis, cross-organizational technical leadership, high-speed SerDes circuitry knowledge, advanced packaging/chiplet integration, matching and parasitic control methodologies
Preferred skills
Experience with UCIe/BoW standards, FinFET/GAA technologies, mentoring senior engineers, governing distributed teams
Technologies
Cadence Virtuoso, Siemens/Mentor Calibre, Ansys Totem, Cadence Voltus, SKILL, TCL, Python, Perl
Responsibilities
Define top-level analog front-end floorplans and integration strategies, establish matching and isolation methodologies, lead technical execution across multiple blocks and partners, drive physical verification and production signoff, create reusable layout methodologies and automation flows, mentor senior engineers, govern technical delivery with contractors and vendors
Seniority
Principal, hands-on IC with strategic leadership
