Senior SerDes & Analog Layout Design Engineer
Core
Drive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies, from floorplanning through tapeout, signoff, and integration.
Role type
Senior IC analog layout engineer (D2D SerDes)
Builds
Production-ready D2D analog front-end IP and SoC integration views
Domain
Semiconductor / Analog Mixed-Signal / Die-to-Die Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal layout, D2D interface design, physical verification (DRC/LVS/ERC), advanced-node process knowledge (5nm/3nm), matching and parasitic control, floorplanning, EMIR/reliability analysis, scripting (SKILL/TCL/Python), cross-block integration, mentorship
Preferred skills
UCIe/BoW standards, advanced packaging/chiplet integration, Cadence APR flows, FinFET/GAA technologies, distributed team management
Technologies
Cadence Virtuoso, Siemens/Mentor Calibre, Ansys Totem, Cadence Voltus, SKILL, TCL, Python
Responsibilities
Own top-level D2D analog front-end floorplanning and integration; establish matching and parasitic-control strategies; lead layout execution across multiple blocks; resolve layout risks for high-speed circuitry; own physical verification and signoff closure; develop layout methodologies and automation flows; provide technical guidance and mentorship; coordinate technical execution with distributed teams and partners.
Seniority
Senior, hands-on IC with leadership responsibilities