Senior Silicon Design Engineer
Core
Own development of custom IPs from microarchitecture to RTL implementation, verification, and post-silicon validation, driving PPA optimization and hardware acceleration.
Role type
Senior Silicon Design Engineer (IP Development)
Builds
Custom hardware IPs and high-performance data processing accelerators
Domain
Semiconductor / Digital Logic Design
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog/Verilog/VHDL), microarchitecture specification, synthesis and static timing analysis (STA), timing closure, CDC/RDC/LINT/LEC, Python/Perl/C/C++/C#, high-speed CMOS design, AMBA AXI protocols, pre/post-silicon debug
Preferred skills
Mentorship, design excellence methodology, automation
Technologies
SystemVerilog, Verilog, VHDL, Python, Perl, C, C++, C#, AMBA AXI
Responsibilities
Develop custom IPs from microarchitecture to RTL; Lead design signoff activities (CDC, RDC, LINT, synthesis, STA); Design leading edge hardware algorithms; Drive pre-silicon and post-silicon debug and silicon bring-up; Mentor engineers and champion design excellence
Seniority
Senior, hands-on IC
