Principal Design Engineer
Core
Leading high-performance, high-bandwidth digital design for IP microarchitecture, RTL, synthesis, and SoC integration.
Role type
Principal Design Engineer (Digital ASIC/SOC)
Builds
IP blocks, ASICs, and System on Chip (SoC) subsystems
Domain
Semiconductor / Digital Design / SoC
Deliverable
production ML models | product features | infrastructure
Required skills
Microarchitecture specification, RTL design (Verilog/System Verilog), Synthesis, Timing constraints, PPA trade-offs, Post-Silicon Debug, Fabric/NoC design, CPU/graphics core design, Complex algorithmic design for AI, Script development
Preferred skills
D2D IP design experience
Technologies
Verilog, System Verilog
Responsibilities
Develop IP microarchitecture specifications, perform RTL design and synthesis, integrate subsystems into SoC, collaborate with architecture/verification/physical design teams, ensure design implementation and verification to spec
Seniority
Principal, hands-on IC
