Principal Subsystem Design Engineer
Core
Lead the design, integration, and verification of high-performance, complex SoC memory subsystems, driving solutions from architecture through silicon bring-up.
Role type
Principal Subsystem Design Engineer (Memory/SoC)
Builds
High-performance SoC subsystems including PCIe, HBM, imaging, control, interconnect fabrics, and DMA engines
Domain
Semiconductor / Hardware Design / SoC Architecture
Deliverable
production ML models | product features
Required skills
Microarchitecture specification, RTL development (Verilog/SystemVerilog), Design verification, Synthesis, Timing constraints, PPA optimization, Post-silicon debug, DFT, Cross-functional leadership, Agile execution, Scripting (Python/Perl)
Preferred skills
Experience with AI/ML SoCs, Experience with CPUs/VPUs/GPUs/DMA/Tensor units, Experience with AMBA AXI/CHI protocols, Experience with NoCs
Technologies
Verilog, SystemVerilog, Python, Perl, PCIe, HBM, AMBA AXI/CHI, NoC
Responsibilities
Lead design and integration of memory subsystems, Mentor engineers and conduct design/code reviews, Debug complex system-level issues across simulation and silicon, Drive IP reuse across platforms, Collaborate with Architecture, RTL, DV, PD, and Firmware teams
Seniority
Principal, hands-on IC with strategic leadership
