Principal Memory Subsystem Engineer (Design or DV)
Core
Provide technical leadership for high-performance Memory Subsystem development, driving solutions from architecture through silicon bring-up for complex SoCs.
Role type
Principal Memory Subsystem Engineer (Design or DV)
Builds
Custom IP and SoC solutions featuring memory technologies, interconnect fabrics, and high-throughput data buffering.
Domain
Semiconductor / Hardware Design / SoC
Deliverable
production ML models | product features | infrastructure
Required skills
Microarchitecture specification, RTL development (Verilog/SystemVerilog), UVM-based constrained-random verification, CDC/Lint closure, Synthesis and timing constraints, PPA trade-offs, Post-silicon debug, Cross-functional team leadership, Formal property verification, Scripting (Python/Perl), DFT implementation.
Preferred skills
Experience with PCIe, HBM, imaging subsystems, NoCs, DMA engines, AI/ML SoCs, CPUs, VPUs, GPUs, Tensor units.
Technologies
Verilog, SystemVerilog, UVM, C++, Python, Perl, AMBA AXI/CHI, PCIe, HBM, NoC, DFT tools.
Responsibilities
Lead design, integration, and verification of memory subsystems; Develop and optimize subsystem architectures; Mentor engineers and establish best practices; Debug complex design and system-level issues across simulation, emulation, and silicon; Drive execution in an Agile development environment.
Seniority
Principal, hands-on IC with strategic leadership
