Design Verification Engineer
Core
Drive, define, and utilize industry leading design verification methodologies, tools, and flows to ensure differentiated SoCs and IP meet functional and quality specifications.
Role type
Senior IC design verification engineer (SoC/IP)
Builds
Embedded processors, multimedia IPs, vision IPs, data movement IPs, interconnect, safety, security, and realtime functionality
Domain
Semiconductor / SoC design / Embedded processors
Required skills
C/UVM testbenches, constrained-random stimulus, functional coverage, Verilog, AMBA protocols (AXI, CHI, AHB, APB), OCP, simulation tools (NCsim), debug tools, SystemVerilog, VHDL, Tcl, Perl, Python, ATE, bench characterization
Preferred skills
Digital design methodologies, sparse legacy documentation navigation, cross-functional collaboration, schedule management, systematic problem-solving, silicon bring-up, deep learning accelerators, DSPs, ARM/RISC-V compute cores, vision analytics, security, multimedia
Technologies
UVM, C, Verilog, SystemVerilog, VHDL, Tcl, Perl, Python, NCsim, ATE, AXI, CHI, AHB, APB, OCP, DMA, Cache, DDR
Responsibilities
Architecting and developing module and system-level test strategies, performance validation, verification plans, testbenches, functional models, and test cases. Promoting and advancing verification methodologies for complex digital logic using C/UVM testbenches. Creating, executing, enhancing, and debugging simulation test cases using coverage-driven, constrained-random stimulus. Defining and implementing functional coverage and driving coverage closure. Debugging complex designs to identify the root cause of problems. Collaborating across verification teams to promote the reuse of components. Verifying SoCs in emulation environments and performing post-silicon verification, characterization, and debug.
Seniority
Senior, hands-on IC
