Senior Design Verification Engineer
Core
Deliver premium-quality custom IP and SoC designs by planning and executing complex verification strategies for high-performance functions.
Role type
Senior Design Verification Engineer (SoC/CPU IP)
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments and tape-out ready designs)
Required skills
Constrained-random verification, SystemVerilog, UVM, Formal verification (SVA), C/C++ test development, Functional coverage closure, RTL debugging, Computer architecture knowledge, Python or Perl scripting
Preferred skills
Debugging in simulation/emulation environments, Experience with complex CPU or SoC IP delivery
Technologies
SystemVerilog, UVM, SVA, Python, Perl, Verilog
Responsibilities
Plan verification test scenarios for complex design IP/SoC, Create and enhance constrained-random verification environments, Develop tests using UVM or C/C++, Analyze and debug test failures with designers, Identify and write functional coverage for stimulus and corner cases, Close coverage to meet tape out requirements
Seniority
Senior, hands-on IC
