Senior Silicon Engineer
Core
Design, verify, and validate analog circuit components for custom SerDes interface IP, including PLLs, clock distribution, and transmit/receive macros, with a focus on mixed-signal validation and timing model generation.
Role type
Senior Silicon Engineer (Analog/Mixed-Signal)
Builds
Custom SerDes interface IP blocks for high-speed data transmission
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog circuit design, Mixed-signal validation, Timing model generation, Behavioral modeling (System Verilog, LEC), Post-silicon validation, Layout optimization, Debugging calibration issues, Scripting (Python, Perl)
Preferred skills
Experience with deep sub-micron nodes, Analog behavioral modeling of PLL components
Technologies
System Verilog, LEC, Python, Perl
Responsibilities
Design and verify analog circuit components for SerDes IP, perform mixed-signal validation of blocks, generate timing models for analog interfaces, coordinate with layout designers, review DV waveforms, and conduct post-silicon validation.
Seniority
Senior, hands-on IC