India-DFT Engineer
Core
Design and implement DFT architectures and methodologies for next-generation SoCs to ensure functionality, reliability, and manufacturability of integrated circuits.
Role type
Senior IC DFT Engineer
Builds
Next-generation System on Chips (SoCs) for high-performance computing accelerators
Domain
Semiconductor / Hardware Design / High-Performance Computing
Required skills
DFT methodology, Scan compression, MBIST, Boundary scan (IEEE 1149.1/6), IEEE 1687, fault models, EDA tools (Synopsys FusionCompiler, TestMax, Mentor Tessent), scripting (Python, TCL), IC design flows, RTL/gate-level simulation
Preferred skills
Experience with advanced process nodes, tape-out success, cross-functional collaboration
Technologies
Synopsys FusionCompiler, TestMax, Mentor Tessent, Python, TCL, Makefile
Responsibilities
Define DFT Architecture and Methodologies for next generation SoCs; Perform scan, MBIST, Boundary scan insertion; Develop high quality tests to verify DFT functionality; Analyze fault models and optimize for high coverage; Work with cross functional teams to develop and verify DFT structures; Collaborate with Test Engineering for test program development and Silicon bring up.
Seniority
Senior, hands-on IC
