Senior ASIC Physical Design Engineer
Core
Senior ASIC Physical Design Engineer responsible for timing closure, synthesis, floorplanning, and signoff of complex, high-performance integrated circuits.
Role type
Senior IC ASIC Physical Design Engineer
Builds
High-performance ASIC products and platforms
Domain
Semiconductor / VLSI / ASIC Physical Design
Required skills
Static timing analysis, Timing constraints management, Synthesis, Formal verification, Floorplanning, Chip partitioning, ECO implementation, EDA tools (Synopsys/Cadence), Scripting (Perl/Python/Tcl)
Preferred skills
Hierarchical timing analysis, Advanced process technologies, Flow automation development, Technical leadership
Technologies
Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, LEC
Responsibilities
Perform static timing analysis at partition and full-chip levels, Drive timing closure for setup/hold/clock/I/O/test, Create and maintain timing constraints and budgets, Perform synthesis and netlist quality checks, Support chip partitioning and floorplanning, Develop flow automation and methodology improvements, Provide technical guidance and mentoring to less-experienced engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
