Principal Signal Integrity Engineer
Core
Perform high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for cutting-edge networking product design.
Role type
Principal Signal Integrity Engineer (High-Speed ASIC/Networking)
Builds
High-speed networking ASICs and PCBs with PAM4 SerDes channels
Domain
Networking / High-Speed Digital Design
Required skills
ASIC PAM4 SerDes analysis, Channel margin analysis (COM), PCB timing analysis, DVT measurements, PLL design and debug, PDN optimization, CPM modeling, 200G line rate experience
Preferred skills
Ansys HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB, Vector Network Analyzers, Time Domain Reflectometers, Phase noise Analyzers, 200G ASIC PAM4 experience
Technologies
PAM4, SerDes, ASIC, PCB, PDN, PLL, Ansys, MATLAB
Responsibilities
Perform COM channel margin analysis to provide design trade-offs amongst ASIC package, board, and connectors; Correlate ASIC PAM4 SerDes simulation results with measurements and work with vendors to improve model accuracy; Perform PCB timing analysis and develop layout/SI design rules; Perform SI DVT measurements on boards and correlate simulations with measurements; Provide technical assessment of projects to SI management team.
Seniority
Principal, hands-on IC
