Senior ASIC Design Verification Engineer - Slingshot
Core
Senior ASIC Design Verification Engineer responsible for pre-silicon verification of HPE Slingshot interconnect ASICs for HPC and AI systems.
Role type
Senior IC ASIC Design Verification Engineer
Builds
High-performance switch and NIC ASICs for HPC and AI data centers
Domain
Semiconductor / High-performance networking / HPC & AI infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM/OVM methodologies, testbench development, coverage closure, regression analysis, bug triage, scripting/automation, mentoring
Preferred skills
High-speed networking/NIC ASIC verification, agentic AI workflows, Python/Perl/Tcl in Linux
Technologies
SystemVerilog, UVM, OVM, EDA tools, FPGA tools, Python, Perl, Tcl, Linux
Responsibilities
Define verification methodology, develop testbenches and bus functional models, implement scoreboards/checkers, manage coverage closure, triage regression failures, apply AI-assisted tools, mentor junior staff
Seniority
Senior, hands-on IC with mentorship responsibilities
