ASIC Principal Engineer
Core
Define and architect high-performance blocks for advanced networking ASICs, focusing on micro-architecture, logic design, timing analysis, and collaboration with verification and physical design teams.
Role type
Principal ASIC Engineer (Networking)
Builds
High-performance networking ASICs
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog RTL coding, ASIC micro-architecture design, logic design, timing constraint analysis, ASIC debugging, high-speed serial interface knowledge, multi-domain clock synchronization
Preferred skills
Synopsys Design Compiler, Verplex LEC, Spyglass, Ethernet/FCoE protocol design, high-performance memory subsystems, leadership
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, Spyglass
Responsibilities
Architect high-performance blocks for networking ASICs, perform micro-architecture and logic design for maximum throughput and minimum power, collaborate on testplan development and debugging, develop timing constraints and perform timing fixes
Seniority
Principal, hands-on IC with strategic oversight
