ASIC Principal Engineer
Core
Define and architect high-performance blocks for advanced networking ASICs, focusing on micro-architecture, logic design, and timing analysis to deliver maximum throughput with minimum power.
Role type
Principal ASIC Engineer (Networking)
Builds
High-performance networking ASICs
Domain
Semiconductor / Networking Hardware
Required skills
Verilog RTL coding, ASIC micro-architecture design, logic design, timing constraint analysis, ASIC debugging, high-speed serial interface design, multi-domain clock synchronization
Preferred skills
Synopsys Design Compiler, Verplex LEC, Spyglass, Ethernet/FCoE protocol design, high-performance memory subsystems, leadership
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, Spyglass
Responsibilities
Architect high-performance blocks for networking ASICs, perform micro-architecture and logic design, collaborate with verification teams on test plans and debugging, collaborate with physical design teams on timing constraints and fixes
Seniority
Principal, hands-on IC with mentorship
