ASIC Design Engineer 2
Core
Design high-speed ASICs for networking chips, handling micro-architecture, RTL coding, timing closure, and debugging.
Role type
Junior ASIC Design Engineer
Builds
High-density networking chips for routers and switches
Domain
Semiconductor / Networking
Required skills
System Verilog, Digital Logic Design, RTL Coding, Timing Closure, EDA Tools, Functional Coverage/SVA
Preferred skills
Computer Architecture, Networking Protocols, Python/Perl
Responsibilities
Develop micro-architecture from functional specifications, write RTL code, perform timing closure, debug verification issues, use EDA tools for design checks.
Seniority
Junior, entry-level IC
