SoC RTL Design- Staff Engineer
Core
Designing System-on-Chip (SoC) micro-architecture and RTL logic for ASICs, focusing on low-power, multi-clock, and asynchronous interfaces.
Role type
Staff SoC RTL Design Engineer
Builds
System-on-Chip (SoC) designs for mobile and consumer electronics
Domain
Semiconductor / Hardware Engineering / ASIC Design
Required skills
SoC design and integration, Verilog/System-Verilog, AMBA protocols (AXI, AHB, APB), USB/PCIe/SDCC peripherals, Memory controller design, Timing closure, Synthesis, Multi-clock and asynchronous interface design, ASIC development tools (Lint, CDC, Design Compiler, Primetime)
Preferred skills
Microprocessor design, Pad ring creation, Chip-level floorplan collaboration, 10-15 years of digital front-end ASIC/RTL design experience
Technologies
Verilog, System-Verilog, Design Compiler, Primetime, Lint, CDC
Responsibilities
Develop RTL code for SoC micro-architecture, perform constraint development and timing closure, collaborate with verification teams for pre/post Silicon debug, design low-power SoC architectures, work with floorplan teams on pad rings
Seniority
Staff, hands-on IC
