Principal ASIC Verification Engineer
Core
Lead block-level or subsystem verification for high-speed networking ASICs, from test plan creation to coverage closure, ensuring functional correctness of complex SoC designs.
Role type
Principal ASIC Verification Engineer (Networking Silicon)
Builds
High-density networking chips (routers and switches) used in HPE Networking edge-to-cloud infrastructure.
Domain
Networking hardware / Silicon design / ASIC verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, constraint-driven random testing, functional coverage, assertions (SVA), simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa), waveform debugging, test planning
Preferred skills
Networking ASIC verification (packet processing, forwarding engines), high-speed interconnects, emulation environments, low-power (UPF), formal verification, post-silicon bring-up
Technologies
Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UVM, SystemVerilog
Responsibilities
Own and drive block-level/subsystem verification efforts from test plans to coverage closure; Develop and maintain advanced UVM verification environments; Perform constraint-driven random testing and debug complex SoC designs; Analyze simulation results and debug waveforms; Collaborate with cross-functional teams to resolve design issues
Seniority
Principal, hands-on IC with strategic ownership
