Principal ASIC Verification Engineer
Core
Own and drive block-level or subsystem verification efforts for high-speed networking ASICs, from creating test plans to achieving comprehensive coverage closure.
Role type
Senior IC ASIC Verification Engineer
Builds
High-speed networking chips (routers and switches)
Domain
Networking hardware / Silicon design
Required skills
SystemVerilog, UVM methodology, constraint-driven random testing, functional coverage, assertions (SVA), simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa), waveform debugging
Preferred skills
Networking ASIC verification (packet processing, forwarding engines), high-speed interconnects, emulation environments, low-power (UPF), formal verification, post-silicon bring-up
Technologies
Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UVM, SystemVerilog
Responsibilities
Develop and maintain advanced UVM verification environments; Perform constraint-driven random testing and debug complex SoC designs; Analyze simulation results and debug waveforms; Collaborate with cross-functional teams to resolve issues; Own verification from test plan to coverage closure
Seniority
Senior, hands-on IC
