ASIC Verification Engineer
Core
Own and drive block-level or subsystem verification efforts for high-speed networking ASICs, from test plan creation to coverage closure.
Role type
Senior IC ASIC Verification Engineer
Builds
High-speed networking chips (routers and switches)
Domain
Networking hardware / Silicon design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (Verification environments and validation)
Required skills
SystemVerilog, UVM methodology, constraint-driven random testing, functional coverage, assertions (SVA), simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa), waveform debugging
Preferred skills
Networking ASIC verification (packet processing, forwarding engines), high-speed interconnects, emulation environments, low-power (UPF), formal verification, post-silicon bring-up
Technologies
Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UVM, SystemVerilog
Responsibilities
Develop and maintain advanced UVM verification environments; Perform constraint-driven random testing and debug complex SoC designs; Analyze simulation results and debug waveforms; Collaborate with cross-functional teams to resolve issues and ensure deliverable quality.
Seniority
Senior, hands-on IC
