ASIC Verification Engineer
Core
Architect and develop block-level verification environments for next-generation ASICs in core routers, switches, and firewalls using SystemVerilog and UVM.
Role type
ASIC Verification Engineer
Builds
High-speed ASICs for large, complex networking systems (routers, switches, firewalls)
Domain
Networking hardware / Semiconductor verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, Perl/Tcl scripting, ASIC debugging, functional coverage analysis, gate-level simulation
Preferred skills
Constrained-random verification, OVM/VMM, Ethernet protocol verification
Technologies
VCS, NC, SystemVerilog, UVM, Perl, Python, Shell
Responsibilities
Architect and develop block-level verification environments for sub-system and full-chip; Define, code, and deliver verification suites/tests for ASICs; Verify large ASIC blocks independently and sign off for tape-out; Work with logic designers to resolve bugs and assist software developers in bring-up development; Develop scripts to improve verification infrastructure
Seniority
Mid-level IC Engineer (3+ years experience)
